As microelectronic devices become highly integrated, problems associated with degradation characteristics may arise. Examples of these problems for a transistor may include short channel effects, Drain Induced Barrier Lowering, subthreshold swing, increased leakage current, as well as increased parasitic capacitance between the junction region and the substrate.
Non-planar transistors, that is, transistors where the channel is defined on surfaces of a three dimensional body, typically in the form of a fin (such as, for example, the fin in a FinFET transistor including either a double-gate, an independent gate, or a trigate transistor), have been proposed in order to address many of the above integration problems. However, the introduction of non-planar transistors has introduced its own particular problems, such as, for example, corner effects, the difficulty of fabricating fins with high aspect ratios, floating body effects related to a fin built on an SOI substrate, and self-heating for non-planar transistors built on an SOI substrate, to name just a few.
In addition to the above-mentioned problems sometimes associated with non-planar transistors, one particular issue concerns fringe effects associated with unwanted capacitance between the gate electrode and the fin in a non-planar transistor built on a bulk silicon substrate. In this respect, reference is made to FIG. 1, where a conventional trigate transistor 100 is depicted. As shown in FIGS. 1a and 1b, trigate device 100 includes a substrate body 102 including a fin 104 and a substrate base 106. A device isolation layer 105 is provided on the substrate base 106 of substrate body 102 in order to isolate portions of the substrate body from a gate electrode 110 extending over the fin 104 as shown. Fin 104 includes a device portion 108, which corresponds to the portion of fin 104 extending above dotted indicator line A-A Device portion 108 includes an upper surface 112, and side walls 114 and 116, which together contribute to provide the channel regions of trigate device 100. Surfaces 112,114 and 116 are covered by gate dielectric layer 119, a function of which is to control a capacitance between gate electrode 110 and device portion 108 to thereby control charge flow in the channel region. Dotted indicator line A-A has been provided. on FIGS. 1a and 1b to mark an upper surface of device isolation layer 105 corresponding to a lower demarcation line for device portion 108.
As seen in FIGS. 1a and 1b, disadvantageously, the provision of device isolation layer 105 onto substrate body 102 by way of etching typically results in the formation of side recesses 118 on each side of fin 104 below device. portion 108 as shown. It is noted that FIG. 1b shows a partially cut-off version of the trigate transistor 100, that is, a version where the source and drain portions are not fully shown by virtue of the device portion as having been cut off at the source and drain portions to show the recesses 118. However, general regions of device portion 108 corresponding to the source and drain portions are indicated by arrows as the source and drain regions S and D, respectively. The recesses 118 typically result from an etch process to etch the material of isolation layer 104 to the level of line A-A. When the gate electrode 110 is provided over fin 104, in the presence of recesses 118, the material of the same typically disadvantageously fills recesses 118 forming unwanted recess. electrode portions 120 as shown. The recess electrode portions 120 extending along the sides of fin 104 along a length thereof disadvantageously generate unwanted capacitance with regions of fin 104 extending below the device portion 108. In the presence of such fringe capacitance, fringe effects are disadvantageously observed according to which control of charge flow within the channel region becomes compromised, thus negatively impacting an electrical performance of the device as a whole.
The prior art has failed to provide a simple and effective manner of controlling fringe effects brought about as a result of recess electrode portions in non-planar microelectronic devices built on bulk substrates.